Clock circuits are useful because, typically, they provide synchronization and control signals to a system. Duty-cycle describes the ratio between the pulse duration (τ) and the period (T) of a rectangular waveform such as a clock signal. Duty-cycle of clock signals (for both transmitter and receiver) is important for the communication systems, including the Double Data Rate (DDR) memory interface. The duty-cycle of a clock signal can be adjusted and maintained by using a duty-cycle adjustment loop.
In an electronic integrated circuit (e.g., a memory device, memory controller or processor), if multiple clocks are present, there is typically an individual duty cycle adjustment circuit for each clock. The duty cycle adjustment circuit (excluding the clock generator) for a clock typically consumes considerable die area of the integrated circuit, and often much of this area is for the duty cycle detector circuit. Therefore the duty cycle adjustment circuits for multiple clocks consume or occupy correspondingly large amounts of die area of the integrated circuit.
Furthermore, in typical implementations it is desirable to make the duty-cycle adjustment circuit large to reduce transistor mismatch and improve accuracy. If multiple instances of the duty-cycle adjustment circuit are used on a die, they may be size limited to meet a size limitation on the die, which may limit accuracy of the duty-cycle adjustment circuits.